1. Field of the Invention
The present invention relates to analog-to-digital converters. More specifically, the present invention relates to analog-to-digital converters having delta-sigma modulators.
2. Description of the Related Art
Currently ‘oversampled’ delta-sigma modulator type analog-to-digital (ADC) converters are used for applications (such as audio) requiring accurate conversion of analog signals to digital signals at high speed. Sigma-delta modulator (ADC) converters include a delta-sigma modulator and a digital filter, which processes the output thereof. The delta-sigma modulators allow for the use of low resolution components running at a higher sampling rate to provide a high resolution ADC converter at a lower sampling rate. The delta-sigma modulators allow for lower costs and higher accuracy than could otherwise be achieved without a delta-sigma modulator.
There is an ongoing need to increase the sampling rate (operating frequency) to higher frequencies for digital receivers, radar receivers and other applications requiring high rate ADC conversion.
A digital-to-analog converter (DAC) is typically implemented within the delta-sigma modulator as a feedback element, the precision of which limits the precision of the delta-sigma modulator. The precision of the DAC converter is, in turn, limited by the ability of the designer to match elements in the DAC in the fabrication process. To address this problem, error-shaping techniques are often used in the art to minimize the DAC error effects over the passband of the modulator.
Prior implementations of error shaping or error randomization for the feedback DAC in a continuous-time delta-sigma modulator have required switching or multiplexing circuitry between the ADC and the DAC. The delay through this circuitry is effectively added to the minimum allowable time for a half period, of the sampling clock, and thus reduces the maximum sampling frequency and the achievable signal bandwidth for a given oversampling ratio.
In addition, the extra circuitry between the ADC and the DAC may introduce timing jitter or other timing related errors that would raise the noise floor of the delta-sigma modulator, thereby reducing its dynamic range.
Hence, there is a need in the art for a system or technique for increasing the speed of delta-sigma ADC converters while eliminating the problems associated therewith.